Design-for-test (DFT),1 to 7 yrs Experience – Sasken,Bangalore

Posted on July 23, 2007. Filed under: Design-for-test |

 Design-for-test (DFT)
Exp: 1 – 7 yrs
Location: Bangalore

* Verification of a fullchip or Gate level verification, Formal Verification,Scripting, programming
* Experience in Verilog, VHDL, Modelsim or any Digital design simulator,SOC Verification, Frontend verification Knowledge of VERA / SPECMAN is a big PLUS.

To apply for this position please send your resume to

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