Archive for May 2nd, 2006

Project Engineer / Module Lead / Project lead / Technical Lead / Architect / Project Manager & Domain consultants – Wipro, Kochi

Posted on May 2, 2006. Filed under: Architect, Domain Consultants, Project Leader, Project Manager, VLSI |

Send your CV across to "contact.jobmilan@googlemail.com". This is a referral job and we will send it to the referrer.

Wipro in Kochi with 200+ engineers is the newest & fastest growing Center with the presence of VLSI, Semiconductors, Consumer electronics and Embedded systems Business Units.

Opportunities in – VLSI Service Group in Kochi

 

Project Engineer / Module Lead / Project lead / Technical Lead / Architect / Project Manager & Domain consultants.

 

Skills 1 :  ASIC / SoC / FPGA Design :  Should have good experience in Logic Design & RTL Implementation using Verilog/VHDL. Experience in Logic Synthesis (DC), Static Timing Analysis (Primetime) would desirable. Experience in FPGA, System design or Board design would be preferred.

 

Skills 2 : ASIC Physical design : Should have experience in Semi-custom designs for complex SoC designs and ASICs, involving Physical Synthesis, P&R and Timing closure, Signal Integrity Analysis and Physical Verification. Should have project execution background in latest technology nodes, deep understanding of Physical Design concepts and deep-sub-micron challenges, and experience in one or more of the contemporary Design Methodologies (Cadence/Magma/Synopsys).

 

Skills 3 : Modeling : Should have good experience in C Modeling or any modeling techniques for Chip Sets. Experience in System C / C / C++ programming skills. Should have good analytical and debugging skills.

 

Skills 4 : Design For Test : Should have good experience in Design for Test Methodology Design and Implementation for SoC Designs (Full-scan, Memory BIST, Boundary scan). Should be familiar with any of the DFT Tools (Synopsys / Mentor / Cadence / Magma / LogicVision). Experience in ATPF Functional vector generation and simulation is required. Experience in VHDL / Verilog and Perl scripting would be desirable. Exposure to At-Speed testing, Test compression, scan compression, memory test & repair techniques and JTAG would be an advantage.

 

Skills 5 : Verification : Should have good experience in any of the following skills: Functional Verification of ASIC / FPGA / SoC using Verilog / VHDL / Vera / Specman. Experience on Processor Verification / Validation Techniques is desirable. Knowledge on ARM Processor / Unix shell / Perl scripts & Knowledge on Digital Hardware / Processors would be an advantage.

 

Qualification:BE / BTech / MCA / MTech / MS / MSC
Experience: 2 to 12 years
Work Location: Cochin

 

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Freshers, 2006 Batch – Subex Systems, Bangalore

Posted on May 2, 2006. Filed under: Freshers |

We are hiring  freshers from 2006 batch and referals are invitied  who match our criteria as below:

 Eligibility Criteria

    * BE / ME/ BTech/ MTech /MCA   with minimum overall aggregate of 60% 
    * Computer Science, Information Technology, Electronics & Communication, Telecom Only
    * Passing Out Year: 2006

Process of the event

    * CV's can be sent to "set@subexsystems.com". Last date to forward profiles is 10th May 2006.
    * Short listed candidates will receive a communication on 15th May 2006 notifying them on date, time & venue to appear for the test to be held on 3rd June 2006.
    * Candidates short-listed from the test will be notified by 8th June 2006 to appear for the technical interview starting from 9th June to 30th June.
    * Joining of the offered candidates in July.

NOTE:   

* This is not a walk-in process and only pre-registered candidates with allotted roll numbers will be eligible for written test.   

* To check on the status of resumes forwarded by subexians the list containing short listed candidates appearing for the test/interview will be uploaded on the intranet     on regular intervals. 
 

Important Dates to remember:
 

1.       Last Date to refer resume: 10th May 2006

2.       Written Test: 3rd June 2006

3.       Interview Dates: 9th June – 30th June

4.       Date of Joining: July

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